Siliance

System Design and Validation

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For our system design we assume there is one or more FPGAs (Field Programmable Gate Arrays) developed for use in our system.  The following is the high level process flow for the development and successful deployment of the FPGAs.   Siliance can provide the onsite resources to perform these functions or you can a combined onsite and offshore team to develop some or all of your FPGA.  Don't hesitate to request a quote for any of the development or support work you have in mind.

Board Level Partition

At this phase of the design process decisions are made as to how the PWB will be designed.  It is a detailed product development phase that determines a great deal about the cost, performance and footprint of the final product.  What portion of the functionality will be provided in software and what part of the functionality will be provided using standard parts?  All of these decisions impact the complexity of the board design and layout.  Many of our partners can assist with the technical, power and cost issues that must be made at this stage. 

System Board Level Hardware Design

The board level hardware design takes all of the digital and analog components and chips and carefully lays them out on the printed wiring board (PWB) to optimize performance and minimize quality problems induced by signal integrity (SI) issues.  Siliance has the talent to develop your board level system and if the requirements need an offshore team we work closely with the eInfochips team to execute your project on time and on budget.  Many of our customers use us to develop test fixture to test out their SoC or to provide a manufacturing level test fixture to test their production units.

Signal Integrity and Power

As part of the board layout process, detailed attention needs to be piad to signal integrity (SI) issues.  In today high speed designs SI is a major contributor to  the overall quality of the system. 

 

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