Analog and AMS Design and Validation








Most complex SoCs today have a portion of the chips dedicated to analog and mixed signal circuits and our example case is no exception.  Our typical system requires the development of a System on a Chip (SoC) or an Application Specific Gate Array (ASIC).  siliance can provide you with design and verification skills to supplement your team or we can assemble a competent offshore team to develop some or all of your SoC or ASIC for you.   In the description of the various phases of the chip development below we highlight some of our partner's expertise in the key development areas.  Don't hesitate to request a quote for any of the development or support work you have in mind. 

Analog Design

Sankalp and siliance have extensive analog design services covering from conceptual design through implementation, validation and circuit layout.  We are particularly skilled at lower power designs requiring power management and clocking or high speed interfaces like SERDES.

Analog Simulation/Analysis

We can provide a number of simulation, validation and analysis services.  A brief overview of Samkalp's extensive capabilities is shown here.

Analog IP

Sankalp has and extensive array of analog IP including specific I/O cells and general components which can be briefly reviewed here.

AMS Verification

eInfochips has among the best skills and methodologies available today for verification across analog and digital domains.  They were early adopters of the SystemVerilog verification language and have become worldwide experts in VMM, OVM and now UVM methods.   The eInfochips team also has performed extensive analog-mixed signal verification using some innovative techniques to bridge the digital/analog boundary.

Analog Layout

Sankalp has been successfully doing custom analog layout  for several of the world's largest semiconductor manufactures.  These skills can be provided at the customer's site or completely offshore.  

Analog/Mixed Signal (AMS) Physical Design

eInfochips has a large group of digital and AMS Physical Design engineers including DFT to front end your fabrication or aggregation partner.  


We support the GDSII release to the fabrication vendor or aggregation partner of your choice.  We have worked with every major foundry in the world and with most of the major aggregators. 


Many of the design verification tests can be used as stimulus for the semiconductor test program. 

Pre/Post Silicon Validation & Prototyping

We can support the lab validation of your silicon either at your lab or at our partner's facilities.