Siliance

ASIC/SoC Design and Verification

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Our typical system requires the development of a system on a chip (SoC) or an Application Specific Gate Array (ASIC).  siliance can provide you with design and verification skills to supplement your team or we can assemble a competent offshore team to develop some or all of your ASIC or SoC for you.   In the description of the various phases of the chip development below we highlight some of our partner's expertise in the key development areas.  Don't hesitate to request a quote for any of the development or support work you have in mind.

Digital IP Integration

We can integrate your IP blocks or a third party's IP block or you can select IP from some of our Partner's IP library. 

SIBIZ has a growing list of memory and processor IP blocks for your use.  We can also customize it to exactly fit your requirements.    

eInfochips also has an extensive list of SystemVerilog OVM/UVM compatible verification IP that will plug directly into your OVM testbench.  Or we can make proprietary modification to support your specific needs.  

Digital Design

siliance and eInfochips have extensive skills in digital design in image processing, communications, mobility, consumer electronics and industrial automation.  We can provide individual talent or the entire team.

SIBIZ has extensive design skills in processor design, memory systems design, security systems and communications systems. 

Design Verification

eInfochips has among the best skills and methodologies available today.  They were early adopters of the SystemVerilog verification language and have become worldwide experts in VMM, OVM and now UVM methods.  They also have extensive skills in migrating legacy testbenches designed with SystemC, e or Vera to SystemVerilog.  They utilize the latest methodologies in functional verification and constraint random techniques.  Whether you need to verify an IP block or a system level verification of your top level ASIC or SoC then you should consider using eInfochips. 

The SIBIZ team has an sophisticated methodologies using coverage driven verification techniques to validate their complex ASIC designs.  They have an excellent track record of first pass silicon success.  They specialize in SystemVerilog verification techniques particularly in VMM and UVM methodologies.

Physical Design Services

eInfochips has a large group of digital and AMS Physical Design engineers including DFT to front end your fabrication or aggregation partner.  

Fab

We support the GDSII release to the fabrication vendor or aggregation partner of your choice.

Test

Many of the design verification tests can be used as stimulus for the semiconductor test program. 

Pre/Post Silicon Validation & Prototyping

We can support the lab validation of your silicon either at your lab or at our partner's facilities.

 

 

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