Siliance

FPGA Design and Verification

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For our hypothetical system design we assume there is one or more FPGAs (Field Programmable Gate Arrays) developed for use in our system.  The following is the high level process flow for the development and successful deployment of the FPGAs.   Siliance can provide the onsite resources to perform these functions or you can a combined onsite and offshore team to develop some or all of your FPGA.  Don't hesitate to request a quote for any of the development or support work you have in mind.

Partition

At this phase of the design process decisions are made as to how many FPGAs will be designed.  It is a detailed product planning phase that determines a great deal about the cost, performance and footprint of the final product.  What portion of the functionality will be provided in software and what part of the functionality will be provided using standard parts?  All of these decisions impact the complexity of the FPGA design.  Many of our partners can assist with the technical, power and cost issues that must be made at this stage. 

FPGA Design

Once the FPGA partitioning is completed the FPGA designs can start with the generation of the functional specifications of each of the FPGAs. This spec contains the major blocks in each FPGA and defines the FPGA pinout to interconnect with the functional and test subsystems of the product.  The goals for power and chip utilization capacity are defined at this level as well as the desired floorplan of the FPGA. 

Once the specification is completed and approved the detailed design of the FPGA and the design verification can begin.

P&R Timing

Place and routing of the FPGA and the resultant timing are today some of the most complex and time consuming tasks.  Since FPGAs today are very complex sometimes in excess of millions of logic elements the ability to route all of those components an still achieve the desired performance requires some extensive physical design skills in understanding the structure and floorplan of the FPGA.  These need to be carefully controlled in order to have a successful FPGA.  The FPGA design will depending on how it is structured will either compliment or negatively impact the FPGA physical design.  This is not part of the implementation that you want to outsource to neophytes.  Our partners have had extensive experience with these issues. 

Board Hardware Design

The board level hardware design takes all of the digital and analog components and chips and carefully lays them out on the printed wiring board (PWB) to optimize performance and minimize quality problems induced by signal integrity (SI) issues.  Siliance has the talent to develop your board level system and if the requirements need an offshore team we work closely with the eInfochips team to execute your project on time and on budget.  Many of our customers use us to develop test fixture to test out their SoC or to provide a manufacturing level test fixture to test their production units.

Verification

Several of our partners have among the best skills and methodologies for design verification of logic systems available today.  They were early adopters of the SystemVerilog verification language and have become worldwide experts in VMM, OVM and now UVM methods.  They also have extensive skills in migrating legacy testbenches design with SystemC, e or Vera to SystemVerilog.  They utilize the latest skills in functional coverage driven verification and constraint random techniques.  If you need to verify an FPGA sub-block the complete system verification at the top level of your FPGA then you should consider using einfochips or SIBZ

 

 

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